The present invention relates, in general, to electronics, and more particularly, to semiconductor packages, structures thereof, and methods of forming semiconductor packages.
In general, a lead frame for a semiconductor package is manufactured by mechanically stamping or chemically etching a metal strip. The lead frame serves as a lead connecting a semiconductor die to an external circuit and as a frame that fixes the semiconductor package to the external circuit.
The lead frame can have various shapes according to trends toward high density and high integration of semiconductor dies and component mounting method. In order to electrically connect a semiconductor die and a lead frame, like a memory and a CPU, to each other, in the past the semiconductor package has been configured such that a bond pad of the semiconductor die and the lead frame were connected to each other by wire bonding or using conductive bumps.
The lead frame having the aforementioned configuration was electrically connected to the semiconductor die, followed by encapsulating using an encapsulant, thereby completing the semiconductor package. Several problems exist with such semiconductor packages, including extra manufacturing cost and time to complete the wire bonding or conductive bump processes, increased likelihood of reliability issues caused by damage during such processes, increased package heights, and poor performance including failures in high current applications.
Accordingly, it is desirable to have a method and structure that reduces the cost of connecting a semiconductor die to a leadframe, that reduces the likelihood of damage during manufacturing to improve reliability, and that improves performance in high current applications.
For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. It will be appreciated by those skilled in the art that words, during, while, and when as used herein related to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as propagation delay, between the reaction that is initiated by the initial action. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. The use of word approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or parts, these members, elements, regions, layers and/or parts are not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or part from another member, element, region, layer and/or part. Thus, for example, a first member, element, region, layer and/or part discussed below could be termed a second member, element, region, layer and/or part without departing from the teachings of the present invention.